Neural network hardware accelerator system with zero-skipping and hierarchical structured pruning methods

Abstract

Systems and methods for structured-pruning, zero-skipping and accelerated processing of an artificial neural network (ANN) are described. The ANN may include one or more convolution layers. 2D channels in filters of the convolution layers comprise fully pruned channels (FPCs), each containing only zero weights, and mixed channels (MCs), each containing at least one non-zero weight. At least a portion of the MCs satisfy a limited zero sequence (LZS) condition limiting the number and location of zeroes in the MC. The LZS condition may be based on a number of weights that a zero-skipping circuit of a computing system for processing the ANN is configured to evaluate and skip in a single cycle. Thus, when processing the structurally-pruned ANN using the zero-skipping method, the computing system may avoid processing zero weights. This may allow speeding up the ANN processing and reducing the power required for processing.