The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 29, 2025

Filed:

Feb. 06, 2023
Applicant:

Stmicroelectronics S.r.l., Agrate Brianza, IT;

Inventors:

Gianluca Tortora, Legnano, IT;

Mario Barone, Lombardy, IT;

Assignee:

STMicroelectronics S.r.l., Agrate Brianza, IT;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 29/42 (2006.01); G06F 11/10 (2006.01);
U.S. Cl.
CPC ...
G06F 11/1004 (2013.01); G11C 29/42 (2013.01);
Abstract

A processing system includes configuration registers and a non-volatile memory with memory slots storing configuration data bits and error detection bits. A hardware configuration circuit sequentially reads the data bits from the non-volatile memory for storage in respective configuration registers by: receiving bits from a current memory slot; selectively asserting an error signal in response to comparison of received error detection bits with calculated error detection bits; storing the received bits to temporary registers where the error signal deasserted and other otherwise asserting a further error signal where the error signal is asserted. Otherwise, predetermined configuration data is stored to the temporary registers. The content of the temporary registers is then sequentially stored to the configuration registers. A reset signal is generated in response to the further error signal to reset the configuration registers.


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