Memory controller for a high capacity memory circuit using virtual bank addressing

Abstract

A memory system includes a memory device including an array of storage transistors organized in multiple memory banks, each memory bank including multiple memory pages; and a control circuit configured to interact with the memory device to perform read and write operations. The control circuit includes a read queue configured to store active read requests for reading data from the memory device, a write queue configured to store active write requests for writing data to the memory device, a command selector to select one or more commands issued by the read queue or the write queue, and a virtual to physical address translator to convert the memory address of the selected command encoded with the virtual bank index to a corresponding memory physical addresses, the selected command with the memory physical address being issued to the memory device for execution at the memory device.