The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 29, 2025

Filed:

Feb. 24, 2023
Applicant:

Silicon Laboratories Inc., Austin, TX (US);

Inventors:

Anant Verma, Austin, TX (US);

Rangakrishnan Srinivasan, Austin, TX (US);

Zhongda Wang, San Jose, CA (US);

Assignee:

Silicon Laboratories Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/28 (2006.01); H04B 17/14 (2015.01); H04L 27/12 (2006.01);
U.S. Cl.
CPC ...
G01R 31/2824 (2013.01); H04B 17/14 (2015.01); H04L 27/12 (2013.01);
Abstract

Modulation testing separately enables slices of an analog varactor array of an LC oscillator. For each enabled slice, a reference voltage supplying a resistor ladder is set to a plurality of different reference voltage values. Resistor ladder voltages generated for the different reference voltage values are supplied to the enabled slice and a control voltage coupled to the enabled slice is swept for each of the reference voltage values. Respective frequencies of an oscillator signal coupled to an output of the LC oscillator are measured for each enabled slice for each combination of the reference voltage values and the control voltage values. The linearity of LC oscillator gain is determined for each of the reference voltage values for each slice based on the respective frequencies and the control voltage values. Passing/failing the modulation testing is based on the linearity of the LC oscillator gain.


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