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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12369501 B1

PDFFull Text
Date of Patent:
Jul. 22, 2025

Filed:

Feb. 07, 2024

Systems and methods for fabrication of superconducting integrated circuits

Applicant:

1372934 B.c. Ltd., Burnaby, CA;

Inventors:

Eric Ladizinsky, Manhattan Beach, CA (US);

Jeremy P. Hilton, Vancouver, CA;

Byong Hyop Oh, San Jose, CA (US);

Paul I. Bunyk, Pt. Roberts, WA (US);

Assignee:

1372934 B.C. LTD., Burnaby, CA;

Attorney:

Cozen O'Connor

Primary Examiner:

Paul A Wartalowicz

Int. Cl.
CPC ...
H10N 60/01 (2023.01); B82Y 10/00 (2011.01); H01L 21/285 (2006.01); H01L 21/768 (2006.01); H10N 60/10 (2023.01); H10N 60/12 (2023.01); H10N 60/80 (2023.01); H10N 60/85 (2023.01); H10N 69/00 (2023.01); G06N 10/00 (2022.01);
U.S. Cl.
CPC ...
H10N 60/0912 (2023.02); B82Y 10/00 (2013.01); H01L 21/2855 (2013.01); H01L 21/76877 (2013.01); H01L 21/76891 (2013.01); H10N 60/01 (2023.02); H10N 60/0156 (2023.02); H10N 60/10 (2023.02); H10N 60/12 (2023.02); H10N 60/805 (2023.02); H10N 60/855 (2023.02); H10N 69/00 (2023.02); G06N 10/00 (2019.01);
Abstract

Various techniques and apparatus permit fabrication of superconductive circuits. A niobium/aluminum oxide/niobium trilayer may be formed and individual Josephson Junctions (JJs) formed. A protective cap may protect a JJ during fabrication. A hybrid dielectric may be formed. A superconductive integrated circuit may be formed using a subtractive patterning and/or additive patterning. A superconducting metal layer may be deposited by electroplating and/or polished by chemical-mechanical planarization. The thickness of an inner layer dielectric may be controlled by a deposition process. A substrate may include a base of silicon and top layer including aluminum oxide. Depositing of superconducting metal layer may be stopped or paused to allow cooling before completion. Multiple layers may be aligned by patterning an alignment marker in a superconducting metal layer.

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