The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 22, 2025

Filed:

Nov. 02, 2022
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Sungwook Lee, Seoul, KR;

Sumin Hwangbo, Hwaseong-si, KR;

Sanghyun Kim, Goyang-si, KR;

Yujung Kim, Osan-si, KR;

Jungwook Lee, Yongin-si, KR;

Minwook Choi, Seoul, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 33/50 (2010.01); H10H 20/814 (2025.01); H10H 20/831 (2025.01); H10H 20/851 (2025.01); H10H 20/857 (2025.01); H10H 29/14 (2025.01);
U.S. Cl.
CPC ...
H10H 20/8514 (2025.01); H10H 20/814 (2025.01); H10H 20/8312 (2025.01); H10H 20/857 (2025.01); H10H 29/142 (2025.01);
Abstract

Provided is a semiconductor light emitting device including a base layer, a light emitting structure including a first semiconductor layer having a first conductivity, an active layer, and a second semiconductor layer having a second conductivity different from the first conductivity, a wavelength converting layer on the light emitting structure, a separation wall disposed adjacent to side surfaces of the wavelength converting layer, a first electrode metal layer on a lower surface of the first semiconductor layer, the first electrode metal layer including a reflection structure, and a second electrode metal layer electrically connected to the second semiconductor layer via through holes penetrating the first electrode metal layer, the first semiconductor layer, and the active layer, and exposing the second semiconductor layer, wherein the semiconductor light emitting device is configured to implement gradation in a first direction based on adjusting at least one of the light emitting structure on an upper surface of the second semiconductor layer, the reflection structure, the separation wall, and a structure included in the light emitting structure.


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