The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 22, 2025

Filed:

Mar. 16, 2023
Applicant:

Lodestar Licensing Group Llc, Evanston, IL (US);

Inventor:

Yongjun Jeff Hu, Boise, ID (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10D 30/01 (2025.01); H10B 41/30 (2023.01); H10B 41/35 (2023.01); H10B 43/35 (2023.01); H10B 69/00 (2023.01); H10D 30/69 (2025.01); H10D 64/01 (2025.01);
U.S. Cl.
CPC ...
H10D 30/0413 (2025.01); H10B 41/30 (2023.02); H10B 41/35 (2023.02); H10B 43/35 (2023.02); H10B 69/00 (2023.02); H10D 30/0411 (2025.01); H10D 30/69 (2025.01); H10D 30/694 (2025.01); H10D 64/035 (2025.01); H10D 64/037 (2025.01);
Abstract

Some embodiments include methods of forming charge storage transistor gates and standard FET gates in which common processing is utilized for fabrication of at least some portions of the different types of gates. FET and charge storage transistor gate stacks may be formed. The gate stacks may each include a gate material, an insulative material, and a sacrificial material. The sacrificial material is removed from the FET and charge storage transistor gate stacks. The insulative material of the FET gate stacks is etched through. A conductive material is formed over the FET gate stacks and over the charge storage transistor gate stacks. The conductive material physically contacts the gate material of the FET gate stacks, and is separated from the gate material of the charge storage transistor gate stacks by the insulative material remaining in the charge storage transistor gate stacks. Some embodiments include gate structures.


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