The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 22, 2025

Filed:

May. 26, 2022
Applicant:

Sandisk Technologies Llc, Addison, TX (US);

Inventor:

Akihiro Tobioka, Nagoya, JP;

Assignee:

Sandisk Technologies, Inc., Milpitas, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10B 41/35 (2023.01); G11C 16/04 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01);
U.S. Cl.
CPC ...
H10B 41/35 (2023.02); G11C 16/0483 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 43/10 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02);
Abstract

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory openings vertically extending through the alternating stack, and memory opening fill structures located within a respective one of the memory openings. Composite drain-select-level isolation structures divide each drain-select-level electrically conductive layer into a respective plurality of electrically conductive strips. Each drain-select-level isolation structure includes a respective first drain-select-level isolation material portion vertically extending through each drain-select-level electrically conductive layers and a respective set of second drain-select-level isolation material portions vertically extending through each of the drain-select-level electrically conductive layers and at least a topmost dummy electrically conductive layer that underlies the drain-select-level electrically conductive layers.


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