Memory device using semiconductor element

Abstract

A memory device includes pages in a column direction on a substrate and memory cells in each page in a row direction in plan view. Each memory cell includes a semiconductor base, first and second impurity regions, connected to a source line and a bit line, respectively, at both ends of the semiconductor base, and first and second gate conductor layers, one of which is connected to a word line and the other of which is connected to a plate line. Page erase, page write, and read operations are performed by controlling voltages applied to the source, bit, word, and plate lines. A first operation of outputting data of a first page to an input/output circuit via a sense amplifier circuit and a second operation of reading data of a second page of the same bank as the first page to the bit line are performed in parallel.