The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 22, 2025

Filed:

Oct. 26, 2021
Applicant:

Semiconductor Energy Laboratory Co., Ltd., Atsugi, JP;

Inventors:

Kazunori Watanabe, Tokyo, JP;

Satoshi Yoshimoto, Kanagawa, JP;

Koji Kusunoki, Kanagawa, JP;

Susumu Kawashima, Kanagawa, JP;

Motoharu Saito, Kanagawa, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04N 25/44 (2023.01); G06V 40/13 (2022.01); H04N 25/713 (2023.01); H04N 25/779 (2023.01);
U.S. Cl.
CPC ...
H04N 25/44 (2023.01); G06V 40/1318 (2022.01); H04N 25/713 (2023.01); H04N 25/779 (2023.01);
Abstract

A semiconductor device capable of performing authentication in a short time can be provided. The semiconductor device includes a light-emitting unit and an imaging unit. The imaging unit includes a row driver circuit, and the row driver circuit includes first to m latch circuits (m is an integer greater than or equal to 2) and first to m register circuits. A first start pulse signal is input to a first latch circuit and second start pulse signals are input to first to m latch circuits. Scan signals output from the first to (m−1)-th register circuits are input to the second to m-th latch circuits, respectively. The first latch circuit has a function of outputting one of the first start pulse signal and the second start pulse signal to the first register circuit on the basis of data held, and the second to m-th latch circuits have a function of outputting one of the scan signal and the second start pulse signal to the second to m-th register circuits on the basis of data held.


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