The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 22, 2025

Filed:

Dec. 28, 2023
Applicant:

Paypal, Inc., San Jose, CA (US);

Inventors:

Rema Hariharan, Austin, TX (US);

Sathyamangalam Ramaswamy Venkatramanan, Cupertino, CA (US);

Ashok Srinivasa Murthy, San Jose, CA (US);

Rami El-Charif, San Jose, CA (US);

Assignee:

PAYPAL, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 47/726 (2022.01); H04L 41/5019 (2022.01); H04L 67/1012 (2022.01); H04L 67/1031 (2022.01);
U.S. Cl.
CPC ...
H04L 47/726 (2013.01); H04L 41/5019 (2013.01); H04L 67/1012 (2013.01); H04L 67/1031 (2013.01);
Abstract

A load balancer receives a sequence of requests for computing service and distributes the requests for computing service to a computing node in an ordered list of computing nodes until the computing node reaches its maximum allowable compute capability. Responsive to an indication that the computing node has reached its maximum allowable compute capability, the load balancer distributes subsequent requests for computing service to another computing node in the ordered list. If the computing node is the last computing node in the ordered list, the load balancer distributes a subsequent request for computing service to a computing node other than one of the computing nodes in the ordered list of computing nodes. If the computing node is not the last computing node in the ordered list, the load balancer distributes a subsequent request for computing service to another computing node in the ordered list of computing nodes.


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