The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12368438 B1

Date of Patent:

Jul. 22, 2025

Filed:

Nov. 04, 2023

Logic drive based on standard commodity fpga ic chips using non-volatile memory cells

Applicant:

Icometrue Company Ltd., Zhubei, TW;

Inventors:

Jin-Yuan Lee, Miaoli County, TW;

Mou-Shiung Lin, Hsinchu, TW;

Assignee:

iCometrue Company Ltd., Hsinchu County, TW;

Attorney:

Primary Examiner:

Daniel D Chang

Int. Cl.

CPC ...

H03K 19/1776 (2020.01); G11C 7/00 (2006.01); H01L 23/00 (2006.01); H03K 19/17724 (2020.01); H10B 41/00 (2023.01); H10B 41/30 (2023.01); H10B 61/00 (2023.01); H10B 63/00 (2023.01); H10B 63/10 (2023.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 84/85 (2025.01); H10D 86/00 (2025.01); H10D 89/10 (2025.01); H10N 50/10 (2023.01); H10N 50/85 (2023.01);

U.S. Cl.

CPC ...

H03K 19/1776 (2013.01); H01L 24/00 (2013.01); H03K 19/17724 (2013.01); H10B 41/00 (2023.02); H10B 41/30 (2023.02); H10B 61/00 (2023.02); H10B 63/00 (2023.02); H10D 30/024 (2025.01); H10D 30/62 (2025.01); H10D 84/853 (2025.01); H10D 86/00 (2025.01); H10D 86/201 (2025.01); H10D 89/10 (2025.01); H10N 50/10 (2023.02); H10N 50/85 (2023.02); G11C 7/00 (2013.01); H01L 2224/11 (2013.01); H01L 2224/13111 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/18 (2013.01); H01L 2224/73204 (2013.01); H01L 2924/13091 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/181 (2013.01); H01L 2924/18161 (2013.01); H10B 63/10 (2023.02);

Abstract

A field-programmable-gate-array (FPGA) IC chip includes multiple first non-volatile memory cells in the FPGA IC chip, wherein the first non-volatile memory cells are configured to save multiple resulting values for a look-up table (LUT) of a programmable logic block of the FPGA IC chip, wherein the programmable logic block is configured to select, in accordance with its inputs, one from the resulting values into its output; and multiple second non-volatile memory cells in the FPGA IC chip, wherein the second non-volatile memory cells are configured to save multiple programming codes configured to control a switch of the FPGA IC chip.

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