The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 22, 2025

Filed:

Jul. 28, 2023
Applicant:

Western Digital Technologies, Inc., San Jose, CA (US);

Inventors:

Zhenni Wan, San Jose, CA (US);

Bo Lei, San Jose, CA (US);

Assignee:

SANDISK TECHNOLOGIES, INC., Miltipas, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G11C 16/04 (2006.01); G11C 16/26 (2006.01);
U.S. Cl.
CPC ...
G11C 16/26 (2013.01); G11C 16/0483 (2013.01);
Abstract

A memory device includes a memory block comprising a plurality of memory cells and control circuitry configured to perform a read level acquisition operation to determine optimal read levels for reading a plurality of data states of the plurality of memory cells. To perform the read level acquisition operation, the control circuitry is configured to supply a read level acquisition waveform to the plurality of memory cells, obtain data miss compare (DMC) values for the plurality of memory cells based on the read level acquisition waveform, and identify the optimal read levels for the plurality of data states based on the DMC values. The control circuitry is further configured to perform a read operation on the plurality of memory cells in accordance with the optimal read levels as identified based on the DMC values.


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