Semiconductor element memory device

Abstract

There is provided a columnar semiconductor memory device in which a data retention operation is performed in which voltages applied to a first gate conductor layer, a second gate conductor layer, a first impurity region, and a second impurity region are controlled to retain a group of positive holes, generated by an impact ionization phenomenon or a gate-induced drain leakage current, inside a semiconductor body, and a data erase operation is performed in which the voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity region, and the second impurity region are controlled to discharge the group of positive holes from inside the semiconductor body and the voltage of the semiconductor body is lowered with capacitive coupling with the first gate conductor layer and capacitive coupling with the second gate conductor layer.