Approach to child block pinning

Abstract

A hybrid block pinning optimization system includes a small-block processing module that processes a parent-level hierarchy including a plurality of child-level blocks and places a plurality of initial child-block pins corresponding to the child-level blocks. A child processing module places a logic element at a location within a given child block based on the placement of the initial child pins, discards the plurality of initial child pins while maintaining the location of the logic element, places at least one optimized child pin based at least in part on the location of the at least one logic element, and performs an abstraction operation on the logic element while maintaining the at least one child pin within the child blocks. A hierarchical large block synthesis (hLBS) processing module performs an hLBS operation to dissolve the plurality of child blocks, while maintaining the at least one optimized child pin.