The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 22, 2025

Filed:

Mar. 14, 2024
Applicant:

Arm Limited, Cambridge, GB;

Inventors:

David Alan Boles, Austin, TX (US);

David Joseph Hawkins, Austin, TX (US);

Sandipkumar Ladhani, Austin, TX (US);

Assignee:

Arm Limited, Cambridge, GB;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/0815 (2016.01); G06F 12/0806 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0815 (2013.01); G06F 12/0806 (2013.01);
Abstract

A memory device includes a memory array with first and second memory regions, multiple communication ports and coherency control circuitry. The communication ports couple the memory device to host computers, enabling a first host to write a data block to the second region, write a message, including a data descriptor of the data block, to the first or second region, and write message metadata, associated with the message, to the first region, and also to enable a second host to read the message metadata, the data descriptor and the associated data block. The coherency control circuitry controls coherency of data in the first region, including sending an invalidation request to the second host to invalidate a copy of the message metadata stored in a local cache of the second host. The invalidation request is sent in response to the first host writing the message metadata to the first region.


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