The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 22, 2025

Filed:

Dec. 15, 2021
Applicant:

Movellus Circuits Incorporated, Ann Arbor, MI (US);

Inventors:

Mohammad Faisal, San Francisco, CA (US);

Jeffrey Alan Fredenburg, Chicago, IL;

Assignee:

Movellus Circuits Inc., Ann Arbor, MI (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/10 (2006.01); H01L 25/065 (2023.01); H03L 7/00 (2006.01); H03L 7/081 (2006.01); H03L 7/083 (2006.01); H03L 7/099 (2006.01);
U.S. Cl.
CPC ...
G06F 1/10 (2013.01); H01L 25/0657 (2013.01); H03L 7/00 (2013.01); H03L 7/0816 (2013.01); H03L 7/0818 (2013.01); H03L 7/083 (2013.01); H03L 7/0991 (2013.01); H01L 2924/18161 (2013.01);
Abstract

An integrated circuit (IC) chip including clock generation circuitry to generate a clock signal. Clock interface circuitry is coupled to the clock generation circuitry and includes multiple transmit pins that are distributed across a mounting surface of the IC chip. Each of the multiple transmit pins is configured to transmit a respective version of the clock signal to one or more off-chip devices. Multiple receiver pins are distributed across the mounting surface of the IC chip and correspond to the multiple transmit pins. Each of the multiple receiver pins is configured to receive respective arrival clock signals from the one or more off-chip devices. Delay compensation circuitry is coupled to the clock interface circuitry and includes multiple delay circuits. Each delay circuit is configured to delay a given clock signal fed to a given transmit pin by a given delay value to establish global timing alignment of the arrival clock signals at the one or more external devices.


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