The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 15, 2025

Filed:

Apr. 15, 2022
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Doowon Kwon, Seongnam-si, KR;

Changrok Moon, Seoul, KR;

Kyungtae Lim, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04N 25/79 (2023.01); H01L 23/00 (2006.01); H10F 39/00 (2025.01); H04N 25/78 (2023.01);
U.S. Cl.
CPC ...
H10F 39/809 (2025.01); H01L 24/08 (2013.01); H01L 24/80 (2013.01); H04N 25/79 (2023.01); H10F 39/018 (2025.01); H10F 39/811 (2025.01); H01L 2224/08145 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H04N 25/78 (2023.01);
Abstract

Provided is an image sensor including a first layer including a first semiconductor substrate including a pixel unit in which a plurality of unit pixels are provided, and a first wiring layer provided on the first semiconductor substrate, a second layer including a second semiconductor substrate on which a plurality of transistors configured to operate a global shutter operation are provided, and a second wiring layer provided on the second semiconductor substrate, and provided on the first layer such that the first wiring layer and the second wiring layer oppose each other in a first direction, a plurality of first bonding structures bonding the first layer to the second layer based on a first bonding metal exposed on a surface of the first wiring layer being in contact with a second bonding metal exposed on a surface of the second wiring layer, a third layer including a third semiconductor substrate on which a logic circuit is provided, and a third wiring layer provided on the third semiconductor substrate, and bonded to the second layer such that the second semiconductor substrate and the third wiring layer oppose each other in the first direction, and a plurality of second bonding structures extending from the second wiring layer, and bonding the second layer to the third layer based on a bonding via penetrating the second semiconductor substrate being in contact with a third bonding metal exposed to a surface of the third wiring layer.


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