The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 15, 2025

Filed:

Sep. 25, 2023
Applicant:

Chongqing Gigachip Technology Co., Ltd., Chongqing, CN;

Inventors:

Rongbin Hu, Chongqing, CN;

Can Zhu, Chongqing, CN;

Jianan Wang, Chongqing, CN;

Guangbing Chen, Chongqing, CN;

Dongbing Fu, Chongqing, CN;

Zhengping Zhang, Chongqing, CN;

Zhou Yu, Chongqing, CN;

Zhimei Yang, Chongqing, CN;

Min Gong, Chongqing, CN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 1/47 (2025.01); H03M 1/06 (2006.01); H03M 1/12 (2006.01); H03M 1/36 (2006.01); H03M 1/38 (2006.01); H03M 1/46 (2006.01);
U.S. Cl.
CPC ...
H10D 1/474 (2025.01); H03M 1/0612 (2013.01); H03M 1/124 (2013.01); H03M 1/365 (2013.01); H03M 1/38 (2013.01); H03M 1/462 (2013.01); H10D 1/47 (2025.01);
Abstract

The present disclosure provides a polysilicon resistor, a method for manufacturing the same, and a successive approximation register analog-to-digital converter. A polysilicon resistor includes a first silicon substrate; a first silicon oxide layer disposed on the first silicon substrate; a second silicon substrate disposed on the first silicon oxide layer, wherein an insulating isolation structure extends through the second silicon substrate and divides the second silicon substrate into a plurality of substrate isolation areas separated from each other; a second silicon oxide layer disposed on the second silicon substrate; and a polysilicon resistor layer disposed on the second silicon oxide layer, wherein the polysilicon resistor layer includes a plurality of polysilicon resistor blocks separated from each other, the plurality of polysilicon resistor blocks is arranged in one-to-one correspondence with the plurality of substrate isolation areas, and the plurality of polysilicon resistor blocks are connected in series.


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