The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 15, 2025

Filed:

Dec. 03, 2021
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Giyong Chung, Seoul, KR;

Jae-Bok Baek, Osan-si, KR;

Jaeryong Sim, Suwon-si, KR;

Jeehoon Han, Hwaseong-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 43/40 (2023.01); H01L 23/535 (2006.01); H10B 41/27 (2023.01); H10B 41/41 (2023.01); H10B 43/27 (2023.01);
U.S. Cl.
CPC ...
H10B 43/40 (2023.02); H01L 23/535 (2013.01); H10B 41/27 (2023.02); H10B 41/41 (2023.02); H10B 43/27 (2023.02);
Abstract

A three-dimensional semiconductor memory device includes a first substrate, a peripheral circuit structure with peripheral transistors on the first substrate, a second substrate on the peripheral circuit structure, a lower insulating layer in contact with a side surface of the second substrate, a top surface of the lower insulating layer having a concave profile, a first stack on the second substrate, the first stack including repeatedly alternating first interlayer dielectric layers and gate electrodes, and a first mold structure on the lower insulating layer, the first mold structure including repeatedly alternating sacrificial layers and second interlayer dielectric layers, and a top surface of the first mold structure being at a level lower than a topmost surface of the first stack.


Find Patent Forward Citations

Loading…