The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 15, 2025

Filed:

Jun. 29, 2022
Applicant:

Apple Inc., Cupertino, CA (US);

Inventors:

Neha Goel, Herndon, VA (US);

Murali Narasimha, San Ramon, CA (US);

Sreevalsan Vallath, Dublin, CA (US);

Assignee:

Apple Inc., Cupertino, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04W 76/28 (2018.01); H04W 72/1268 (2023.01); H04W 72/23 (2023.01);
U.S. Cl.
CPC ...
H04W 76/28 (2018.02); H04W 72/1268 (2013.01); H04W 72/23 (2023.01);
Abstract

A processor determines that a UE operates in a DRX cycle including a DRX-on duration followed by a DRX-sleep duration. The processor configures a plurality of periodic uplink CG occasions within the DRX cycle. Each uplink CG occasion supports uplink transmission of a predefined size. The processor reads a data buffer to determine a size of accumulated data. At a given uplink CG occasion, the processor compares the size of accumulated data with an upper threshold data size and a lower threshold data size. Responsive to a first comparison result, the processor transmits the accumulated data over one or more uplink CG occasions starting from the given uplink CG occasion. Responsive to a second comparison result, the processor transmits a BSR at the given uplink CG occasion. Responsive to a third comparison result, the processor transmits neither the accumulated data nor the BSR at the given uplink CG occasion.


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