The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 15, 2025

Filed:

Jul. 26, 2023
Applicant:

Polyvalor, Limited Partnership, Québec, CA;

Inventors:

Seyed Mohammad Noghabaei, Longueuil, CA;

Rafael Radin, Florianopolis-SC, BR;

Yvon Savaria, Montréal, CA;

Mohamad Sawan, Montréal, CA;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H02J 50/00 (2016.01); H02J 50/20 (2016.01); H03F 1/22 (2006.01); H03H 7/40 (2006.01);
U.S. Cl.
CPC ...
H02J 50/001 (2020.01); H02J 50/20 (2016.02); H03H 7/40 (2013.01); H03F 1/223 (2013.01);
Abstract

An optimization method comprising: (a) receiving a target value for power received at an antenna, (b) selecting a number of rectifier stages from a first range, and selecting a rectifier transistor drain current from a second range, (c) determining a computed value of the received power, (d) determining an input voltage at which the computed value of the received power matches the target value, (e) determining an output voltage based on the input voltage, the number of stages, and the transistor drain current, (f) when at least one additional value from the first and/or the second range remains to be selected, incrementing the number of stages and/or the transistor drain current, and repeating steps (c) to (e), and (g) when all values from the first and the second range are selected, determining a final number of stages and a final transistor drain current at which the output voltage is highest.


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