IDiyas

For the Inventor, By the Inventor

The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12362280 B1

PDFFull Text
Date of Patent:
Jul. 15, 2025

Filed:

Oct. 28, 2022

Semiconductor device and method of manufacturing the same

Applicant:

Renesas Electronics Corporation, Tokyo, JP;

Inventor:

Takeshi Kawamura, Tokyo, JP;

Assignee:

Renesas Electronics Corporation, Tokyo, JP;

Attorney:

Sughrue Mion, PLLC

Primary Examiner:

Moin M Rahman

Int. Cl.
CPC ...
H10D 30/60 (2025.01); H01L 21/02 (2006.01); H01L 21/285 (2006.01); H01L 21/3105 (2006.01); H01L 21/311 (2006.01); H01L 21/66 (2006.01); H01L 21/768 (2006.01); H01L 23/48 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01); H01L 23/535 (2006.01); H10D 30/01 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H01L 23/485 (2006.01);
U.S. Cl.
CPC ...
H01L 23/535 (2013.01); H01L 21/02126 (2013.01); H01L 21/022 (2013.01); H01L 21/28518 (2013.01); H01L 21/28568 (2013.01); H01L 21/31055 (2013.01); H01L 21/31111 (2013.01); H01L 21/76802 (2013.01); H01L 21/76805 (2013.01); H01L 21/76834 (2013.01); H01L 21/76843 (2013.01); H01L 21/76852 (2013.01); H01L 21/76889 (2013.01); H01L 21/76895 (2013.01); H01L 21/76897 (2013.01); H01L 22/26 (2013.01); H01L 23/481 (2013.01); H01L 23/5283 (2013.01); H01L 23/53238 (2013.01); H01L 23/53266 (2013.01); H01L 23/53295 (2013.01); H10D 30/021 (2025.01); H10D 30/601 (2025.01); H10D 84/0149 (2025.01); H10D 84/038 (2025.01); H01L 21/76885 (2013.01); H01L 23/485 (2013.01); H01L 2924/0002 (2013.01);
Abstract

An upper surface of a plug (PL) is formed so as to be higher than an upper surface of an interlayer insulating film (PIL) by forming the interlayer insulating film (PIL) on a semiconductor substrate (S), completing a CMP method for forming the plug (PL) inside the interlayer insulating film (PIL), and then, making the upper surface of the interlayer insulating film (PIL) to recede. In this manner, reliability of connection between the plug (PL) and a wiring (W) in a vertical direction can be ensured. Also, the wiring (W) can be formed so as not to be embedded inside the interlayer insulating film (PIL), or a formed amount by the embedding can be reduced.

Find Patent Forward Citations

Loading…