The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 15, 2025

Filed:

Jul. 07, 2022
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Hyeonjeong Hwang, Cheonan-si, KR;

Dongkyu Kim, Anyang-si, KR;

Minjung Kim, Cheonan-si, KR;

Taewon Yoo, Seoul, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/34 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/34 (2013.01); H01L 21/4853 (2013.01); H01L 21/56 (2013.01); H01L 23/3135 (2013.01); H01L 23/49811 (2013.01); H01L 23/49822 (2013.01); H01L 24/16 (2013.01); H01L 2224/16227 (2013.01);
Abstract

A semiconductor package includes: a package substrate; a first semiconductor chip disposed on the package substrate; a heat-dissipation pattern disposed on the first semiconductor chip; a first mold layer disposed on the package substrate and at least partially surrounding the first semiconductor chip and the heat-dissipation pattern; a redistribution layer disposed on the first mold layer; a penetration electrode penetrating the first mold layer and coupled to the package substrate; and a connection pattern disposed on the penetration electrode, and connecting the redistribution layer to the penetration electrode, wherein a top surface of the heat-dissipation pattern and a top surface of the connection pattern are exposed by the first mold layer.


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