The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 15, 2025

Filed:

Dec. 22, 2021
Applicants:

Chengdu Boe Optoelectronics Technology Co., Ltd., Sichuan, CN;

Boe Technology Group Co., Ltd., Beijing, CN;

Inventors:

Haigang Qing, Beijing, CN;

Yunsheng Xiao, Beijing, CN;

Miao Wang, Beijing, CN;

Quanyong Gu, Beijing, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 3/3266 (2016.01); G09G 3/20 (2006.01); G09G 3/36 (2006.01); G11C 19/28 (2006.01); H10K 59/12 (2023.01); H10K 71/20 (2023.01); G09G 3/32 (2016.01);
U.S. Cl.
CPC ...
G09G 3/3266 (2013.01); G11C 19/28 (2013.01); G09G 3/20 (2013.01); G09G 3/32 (2013.01); G09G 3/3674 (2013.01); G09G 2300/0408 (2013.01); G09G 2300/0426 (2013.01); G09G 2310/0243 (2013.01); G09G 2310/0267 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/0289 (2013.01); G09G 2310/08 (2013.01); G09G 2330/021 (2013.01); G11C 19/287 (2013.01); H10K 59/1201 (2023.02); H10K 71/20 (2023.02);
Abstract

A display substrate is disclosed, including a display area and a non-display area. The non-display area has a gate drive circuit including multiple cascaded shift register units. A shift register unit includes an input control circuit and an output circuit. The input control circuit is electrically connected to a clock signal line group, a first power supply line, a second power supply line and an output circuit, the output circuit is electrically connected to the first power supply line and a second power supply line. The input control circuit at least includes an input circuit and a first control circuit. The clock signal line group, the second power supply line, the input control circuit, the output circuit and the first power supply line are arranged sequentially along a first direction. The input circuit is located between the second power supply line and the first control circuit in the first direction.


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