The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 15, 2025

Filed:

Jan. 06, 2023
Applicant:

Nvidia Corporation, Santa Clara, CA (US);

Inventors:

Lucien Dunning, Ramsey, NJ (US);

Seth Schneider, San Jose, CA (US);

Dwayne Swoboda, San Jose, CA (US);

Marko Mitic, San Jose, CA (US);

Adam Zabrocki, Kings Park, NY (US);

Assignee:

NVIDIA Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 21/57 (2013.01); A63F 13/73 (2014.01);
U.S. Cl.
CPC ...
G06F 21/57 (2013.01); A63F 13/73 (2014.09);
Abstract

In examples, a VM may receive and aggregate a first attestation report corresponding to a CPU and a second attestation report corresponding to a GPU. The aggregated data may be provided to an attestation service, which may verify the attestation reports indicate a TCB is to include the VM and GPU state data and is to isolate the GPU state data and the VM from an untrusted host OS. Based at least on the TCB being verified, the VM may perform one or more operations using the TCB. The TCB may include a trusted hypervisor to isolate the VM and GPU state data within the GPU(s) from the untrusted host OS. The trusted hypervisor may prevent the host OS from accessing device memory assigned to the VM based at least on controlling an IOMMU and/or second-level address translation (SLAT) used to access the data.


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