The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 15, 2025

Filed:

Nov. 20, 2023
Applicant:

Honeywell International Inc., Charlotte, NC (US);

Inventors:

Pavel Zaykov, Brno, CZ;

Larry James Miller, Black Canyon City, AZ (US);

Assignee:

Honeywell International Inc., Charlotte, NC (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/28 (2006.01); G06F 12/0806 (2016.01); G06F 13/16 (2006.01);
U.S. Cl.
CPC ...
G06F 13/28 (2013.01); G06F 12/0806 (2013.01); G06F 13/1668 (2013.01); G06F 2212/6042 (2013.01); G06F 2213/28 (2013.01);
Abstract

Examples of computing systems that include I/O device(s) that respect an existing hardware resource partitioning in a modern computing platform are provided. The computing systems include at least one CPU having multiple cores and one or more CPU caches. The computing system also includes a main memory having locations, where each location maps to a set in the one or more CPU caches. A first subset of locations is partitioned for thread(s) of a first application and assigned to non-contiguous memory locations of the main memory. The computing system further includes an I/O device separate from the CPU that is configured to store I/O data in a second subset of locations that are different from the first subset of locations. The second subset of locations are non-contiguous memory locations of the main memory that are separated in address space according to a predefined pattern.


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