Memory management device and method applied to intelligence processing unit

Abstract

A memory management device includes a pre-fetch circuit, a setting circuit and a mapping circuit. The pre-fetch circuit acquires original data via a direct memory access (DMA) circuit, wherein the original data indicates a mapping relation between a first virtual address and multiple physical addresses. The setting circuit analyzes the original data to sequentially map the physical addresses to multiple second virtual addresses including the first virtual address and issues a write request. The mapping circuit stores a mapping relation between the physical addresses and the second virtual addresses as a first mapping table according the write request, and utilizes the first mapping table according to at least one read request corresponding to at least one channel of the DMA circuit to access the memory.