The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 15, 2025

Filed:

Aug. 25, 2023
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Keunsan Park, Suwon-si, KR;

Gyeongmin Kim, Suwon-si, KR;

Joon-Whan Bae, Suwon-si, KR;

Heetak Shin, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/02 (2006.01); G06F 3/06 (2006.01); G06F 11/10 (2006.01); G06F 11/14 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0292 (2013.01); G06F 3/0604 (2013.01); G06F 3/0619 (2013.01); G06F 3/0631 (2013.01); G06F 3/064 (2013.01); G06F 3/0647 (2013.01); G06F 3/0652 (2013.01); G06F 3/0656 (2013.01); G06F 3/0679 (2013.01); G06F 11/1068 (2013.01); G06F 11/1451 (2013.01); G06F 12/023 (2013.01); G06F 2212/1016 (2013.01);
Abstract

A storage device, including: a nonvolatile memory device including a plurality of memory cells; and a controller including an internal buffer including zone buffers, and configured to: allocate a plurality of zones to a storage space, select two or more erase units to be allocated to each zone based on a zone map table, fixedly and sequentially manage logical addresses of data written in the plurality of zones, based on reads for sequential logical addresses being requested by the external host device, read first data corresponding to the sequential logical addresses from the nonvolatile memory device, and output the first data to the external host device, and based on the reads being requested, perform a prefetch operation by reading second data corresponding to next sequential logical addresses, and storing the second data in the internal buffer, without receiving a next read request from the external host device.


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