The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 08, 2025

Filed:

Jun. 10, 2024
Applicant:

Samsung Display Co., Ltd., Yongin-si, KR;

Inventors:

Jinho Kim, Yongin-si, KR;

Namhyoung Kim, Yongin-si, KR;

Jiyong Jung, Yongin-si, KR;

Assignee:

Samsung Display Co., Ltd., Yongin-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 3/00 (2006.01); G06F 3/041 (2006.01); G06F 3/044 (2006.01); G09G 3/3233 (2016.01); H10K 59/131 (2023.01); H10K 59/40 (2023.01); H10K 59/88 (2023.01);
U.S. Cl.
CPC ...
H10K 59/88 (2023.02); G06F 3/0412 (2013.01); G06F 3/04164 (2019.05); G06F 3/0446 (2019.05); G09G 3/006 (2013.01); G09G 3/3233 (2013.01); H10K 59/131 (2023.02); H10K 59/40 (2023.02); G09G 2300/0819 (2013.01); G09G 2300/0842 (2013.01); G09G 2300/0861 (2013.01); G09G 2330/12 (2013.01); G09G 2354/00 (2013.01);
Abstract

A display apparatus may include a substrate including a display area and a peripheral area, pixel circuits in the display area, data lines in the display area and connected to the pixel circuits, first circuit driving signal lines in the peripheral area, and configured to transmit a first circuit driving signal to drive the pixel circuits, a data test pad portion at the peripheral area, and including data test pads connected to the data lines, a pad portion on the peripheral area, and including first circuit pads connected to the first circuit driving signal lines, a first test pad portion at the peripheral area, and including first circuit test pads connected to the first circuit pads, and a second test pad portion at the peripheral area, and including second circuit test pads connected to the first circuit test pads.


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