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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12356722 B1

PDFFull Text
Date of Patent:
Jul. 08, 2025

Filed:

Nov. 14, 2023

Manufacturing method of an oxide semiconductor device

Applicant:

Japan Display Inc., Tokyo, JP;

Inventor:

Yohei Yamaguchi, Tokyo, JP;

Assignee:

Japan Display Inc., Tokyo, JP;

Attorney:

Maier & Maier, PLLC

Primary Examiner:

Nikolay K Yushin

Int. Cl.
CPC ...
H01L 27/12 (2006.01); G02F 1/1333 (2006.01); G02F 1/1368 (2006.01); H10D 30/67 (2025.01); H10D 86/40 (2025.01); H10D 86/60 (2025.01); G02F 1/1343 (2006.01); G02F 1/1362 (2006.01); H10K 59/121 (2023.01); H10K 102/00 (2023.01);
U.S. Cl.
CPC ...
H10D 86/60 (2025.01); G02F 1/133345 (2013.01); G02F 1/1368 (2013.01); H10D 30/6713 (2025.01); H10D 30/6729 (2025.01); H10D 30/6755 (2025.01); H10D 86/423 (2025.01); H10D 86/441 (2025.01); H10D 86/451 (2025.01); H10D 86/471 (2025.01); G02F 1/134363 (2013.01); G02F 1/136295 (2021.01); G02F 1/13685 (2021.01); G02F 2202/10 (2013.01); G02F 2202/104 (2013.01); H10D 30/6731 (2025.01); H10D 30/6734 (2025.01); H10D 30/6745 (2025.01); H10K 59/1213 (2023.02); H10K 2102/00 (2023.02);
Abstract

The purpose of the present invention is to improve reliability of the TFT of the oxide semiconductor. The feature of the invention is: A display device comprising: a substrate including a display area where plural pixels are formed, the pixel includes a first TFT of a first oxide semiconductor, a first gate insulating film is formed under the first oxide semiconductor, a first gate electrode is formed under the first gate insulating film, an interlayer insulating film is formed on the first oxide semiconductor; a drain wiring, which connects with the first oxide semiconductor, and a source wiring, which connects with the first oxide semiconductor, are formed on the interlayer insulating film; the drain wiring or the source wiring is a laminated structure of a second oxide semiconductor and a first metal, the second oxide semiconductor is under the first metal.

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