The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 08, 2025

Filed:

Feb. 14, 2024
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Minsu Seol, Seoul, KR;

Minhyun Lee, Suwon-si, KR;

Junyoung Kwon, Seoul, KR;

Hyeonjin Shin, Suwon-si, KR;

Minseok Yoo, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/67 (2025.01); H01L 21/02 (2006.01); H10D 30/01 (2025.01); H10D 48/36 (2025.01); H10D 62/10 (2025.01); H10D 62/80 (2025.01); H10D 62/83 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 99/00 (2025.01);
U.S. Cl.
CPC ...
H10D 30/6735 (2025.01); H01L 21/02521 (2013.01); H01L 21/02527 (2013.01); H01L 21/02568 (2013.01); H01L 21/0259 (2013.01); H10D 30/01 (2025.01); H10D 30/6757 (2025.01); H10D 48/362 (2025.01); H10D 62/118 (2025.01); H10D 62/80 (2025.01); H10D 62/8303 (2025.01); H10D 62/882 (2025.01); H10D 84/0128 (2025.01); H10D 84/0158 (2025.01); H10D 84/038 (2025.01); H10D 99/00 (2025.01);
Abstract

Disclosed are a field effect transistor and a method of manufacturing the same. The field effect transistor includes a source electrode on a substrate, a drain electrode separated from the source electrode, and channels connected between the source electrode and the drain electrode, gate insulating layers, and a gate electrode. The channels may have a hollow closed cross-sectional structure when viewed in a first cross-section formed by a plane across the source electrode and the drain electrode in a direction perpendicular to the substrate. The gate insulating layers may be in the channels. The gate electrode may be insulated from the source electrode and the drain electrode by the gate insulating layers.


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