The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 08, 2025

Filed:

Jun. 17, 2022
Applicant:

Marvell Asia Pte Ltd, Singapore, SG;

Inventors:

Adi Katz, Ramat Gan, IL;

Moran Noiman, Kiryat Ono, IL;

Yaakov Yehezkel, Rehovot, IL;

Eliya Babitsky, Caesaria, IL;

Assignee:

Marvell Asia Pte Ltd, Singapore, SG;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04J 3/06 (2006.01); H04J 3/16 (2006.01);
U.S. Cl.
CPC ...
H04J 3/0661 (2013.01); H04J 3/0626 (2013.01); H04J 3/0682 (2013.01); H04J 3/1676 (2013.01);
Abstract

A method of reducing jitter in transmission of a timestamp across a clock domain boundary includes storing N timestamps, generated in N successive clock cycles of an origin clock domain, in N parallel buffers in the origin clock domain under control of a modulo-N counter, transmitting outputs of the N parallel buffers across the clock domain boundary into a destination clock domain along with the modulo-N counter, processing the modulo-N counter in the destination clock domain to derive a selection signal that selects a stable timestamp from among the outputs of the N parallel buffers, and outputting the selected stable timestamp. The modulo-N counter may be Gray-coded modulo-N counter to reduce jitter in the modulo-N counter across the clock domain boundary.


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