The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 08, 2025

Filed:

Nov. 12, 2020
Applicant:

Insiava (Pty) Ltd., Pretoria, ZA;

Inventor:

Artur Wilhelm Suntken, Pretoria, ZA;

Assignee:

INSIAVA (PTY) LTD., Pretoria, ZA;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03M 3/04 (2006.01); H03F 3/45 (2006.01); H03M 3/00 (2006.01);
U.S. Cl.
CPC ...
H03M 3/484 (2013.01); H03F 3/45183 (2013.01); H03F 3/45475 (2013.01); H03F 2203/45138 (2013.01); H03F 2203/45631 (2013.01);
Abstract

An amplifier circuit includes a resistor divider (R) comprising n resistive elements, two main nodes defined at each end thereof, two readout nodes (d, d), resistor nodes (q) defined between adjacent resistive elements, and an input current source (I) connected or connectable to the first main node (a). The resistor divider (R) comprises two arrays of addressable switch elements controllable by a feedback signal (s) to be open or closed. The amplifier circuit includes a differential pair of transistors (T, T), wherein source terminals of each of the transistors (T, T) are connected to the second node (b), gate terminals of the transistors (T, T) are connected to input signals (v, v), drain terminals of the transistors (T, T) are connected to current sources (I, I), and bulk terminals of the transistors (T, T) are connected to the readout nodes (d, d). The amplifier circuit functions as a difference amplifier, wherein the bulk terminals affect a threshold of the respective transistors (T, T) so as to add or subtract a differential signal derived from the readout nodes (d, d) of the resistor divider (R) determined by the feedback signal (s).


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