System and method for calibrating weighting errors in split capacitance successive approximation analog-to-digital converters

Abstract

The present disclosure relates to the field of microelectronics and solid-state electronics, and in particular to a calibration system and method for weighting errors brought about by parasitic capacitance in split capacitor-based successive approximation analog-to-digital converters. The method uses an MSB array that does not add additional capacitors, only a switch Sto reduce the comparator design difficulty. Meanwhile, an LSB array may add a calibration DAC array Cincluding a binary array of P-bit unit capacitors, a calibration structure C, and a ground switch S. The calibration structure Cincludes four unit capacitors and two switches Sand S. By controlling the switches Sand Sdifferent capacitance values can be generated to reduce the chip area consumption. This structure can reduce the error to LSB/4 and the weighting error of the ADC, and increases the effective number of bits of the ADC without excessively increasing comparator gain.