The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 08, 2025

Filed:

Jun. 14, 2023
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Joo-Han Kim, Suwon-si, KR;

Beom Kon Kim, Suwon-si, KR;

Woo Wan Wang, Suwon-si, KR;

Dong Hyun Lee, Suwon-si, KR;

Jung Su Han, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/06 (2006.01); H03M 1/10 (2006.01); H03M 1/12 (2006.01); H03M 1/50 (2006.01);
U.S. Cl.
CPC ...
H03M 1/0607 (2013.01); H03M 1/1023 (2013.01); H03M 1/1245 (2013.01); H03M 1/50 (2013.01);
Abstract

A semiconductor device includes a first ADC configured to sample an input signal based on a first clock signal, quantize the input signal with a first gain, and output a plurality of first output signals, and a second ADC configured to sample the input signal based on a second clock signal obtained by delaying the first clock signal, quantize the input signal with a second gain, and output a plurality of second output signals. The device includes a gain mismatch estimator configured to calculate first and second values which are averages of absolute values of the first output signals and the second output signals, and calculate first and second gain correction values using the first and second values. A gain mismatch compensator is configured to output a plurality of corrected first output signals and corrected second output signals, according to the first and second gain correction values.


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