The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 08, 2025

Filed:

Aug. 30, 2023
Applicant:

Samsung Display Co., Ltd., Yongin-si, KR;

Inventors:

Jin Sung An, Seongnam-si, KR;

Seok Je Seong, Seongnam-si, KR;

Ji Seon Lee, Hwaseong-si, KR;

Se Wan Son, Yongin-si, KR;

Assignee:

SAMSUNG DISPLAY CO., LTD., Yongin-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 3/32 (2016.01); H01L 25/16 (2023.01); H10H 20/817 (2025.01); H10H 20/857 (2025.01); H10K 59/131 (2023.01);
U.S. Cl.
CPC ...
H01L 25/167 (2013.01); G09G 3/32 (2013.01); H10H 20/817 (2025.01); H10H 20/857 (2025.01); H10K 59/131 (2023.02); G09G 2300/0426 (2013.01); G09G 2310/0267 (2013.01); G09G 2310/0275 (2013.01);
Abstract

A display device includes a substrate, a polycrystalline semiconductor layer including a channel of a driving transistor, and a channel of a seventh transistor, a gate electrode of the driving transistor overlapping the channel thereof, a gate electrode of the seventh transistor overlapping the channel thereof, an oxide semiconductor layer including a channel of a fourth transistor, a gate electrode thereof overlapping the channel of the fourth transistor, a first initialization voltage line connected to a first electrode of the fourth transistor, the first initialization voltage line and the gate electrode of the fourth transistor being position on a same layer, and a second initialization voltage line connected to a second electrode of the seventh transistor, the second initialization voltage line and the first initialization voltage line being positioned on different layers from each other.


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