The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 08, 2025

Filed:

Nov. 09, 2022
Applicant:

Nanya Technology Corporation, New Taipei, TW;

Inventor:

Shing-Yih Shih, New Taipei, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/538 (2006.01); H01L 21/48 (2006.01); H01L 23/00 (2006.01); H01L 25/10 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5381 (2013.01); H01L 21/486 (2013.01); H01L 23/5385 (2013.01); H01L 23/5386 (2013.01); H01L 24/08 (2013.01); H01L 24/80 (2013.01); H01L 25/105 (2013.01); H01L 24/16 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 2224/08235 (2013.01); H01L 2224/16235 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H01L 2225/1023 (2013.01); H01L 2225/1041 (2013.01); H01L 2225/1058 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1434 (2013.01); H01L 2924/3512 (2013.01); H01L 2924/37001 (2013.01);
Abstract

The present application provides a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first die; a first redistribution structure positioned on the first die; a second die positioned on the first redistribution structure and comprising a first cache unit; and a third die positioned on the first redistribution structure, separated from the second die, and comprising a second cache unit. The first redistribution structure comprises: a plurality of conductive layers electrically coupled the first die and the first cache unit of the second die and electrically coupled the first die and the second cache unit of the third die, respectively and correspondingly; and a bridge layer electrically isolated from the plurality of conductive layers, electrically connected the second die and the third die. The first cache unit of the second die and the second cache unit of the third die are topographically aligned with the first die. The first die is configured as a cache memory, and the second die and the third die are configured as logic dies.


Find Patent Forward Citations

Loading…