The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 08, 2025

Filed:

Aug. 02, 2022
Applicant:

Frontgrade Technologies Inc., Colorado Springs, CO (US);

Inventors:

Sean Thorne, Colorado Springs, CO (US);

Mike Newman, Haywards Heath, GB;

Assignee:

FRONTGRADE TECHNOLOGIES INC., Colorado Springs, CO (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/538 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2023.01); H01L 25/16 (2023.01); H01L 21/48 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5381 (2013.01); H01L 21/563 (2013.01); H01L 23/5386 (2013.01); H01L 24/16 (2013.01); H01L 24/17 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 24/81 (2013.01); H01L 24/94 (2013.01); H01L 25/0655 (2013.01); H01L 25/16 (2013.01); H01L 21/4846 (2013.01); H01L 2224/1601 (2013.01); H01L 2224/16221 (2013.01); H01L 2224/1703 (2013.01); H01L 2224/32221 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/81203 (2013.01); H01L 2224/81908 (2013.01); H01L 2224/94 (2013.01);
Abstract

Systems, apparatuses, semiconductor products and methods for semiconductor packages, specifically under chip bridge system-in-packages, are provided that allow one or more bridges to connect two or more dies. For example, high density connections of two or more dies may be connected with an under chip bridge, all of which may be placed on a substrate to form a system-in-package semiconductor package. Various embodiments include methods of manufacturing such packages that include utilizing a flat semiconductor along with bumping operations that may use single sizes of bumping.


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