The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 08, 2025

Filed:

May. 09, 2022
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Haemin Lee, Seoul, KR;

Byoung-Taek Kim, Seongnam-si, KR;

Hyeonjoo Song, Hwaseong-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 43/27 (2023.01); H01L 23/535 (2006.01); H10B 43/40 (2023.01); H10D 88/00 (2025.01);
U.S. Cl.
CPC ...
H01L 23/535 (2013.01); H10B 43/27 (2023.02); H10B 43/40 (2023.02); H10D 88/00 (2025.01);
Abstract

Disclosed are three-dimensional (3D) semiconductor memory devices and electronic system including the same. The 3D semiconductor memory device may include a substrate including first and second regions, a stack structure including interlayer dielectric layers and gate electrodes alternately and repeatedly stacked on the substrate and having a stepwise structure on the second region, a mold structure adjacent to the stack structure on the first region and including interlayer dielectric layers and sacrificial layers alternately and repeatedly stacked on the substrate, a first separation structure crossing the stack structure and extending along a first direction from the first region toward the second region, and a second separation structure crossing the mold structure and extending in the first direction on the first region. A level of a top surface of the first separation structure may be higher than a level of a top surface of the second separation structure.


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