The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 08, 2025

Filed:

Apr. 29, 2021
Applicants:

Chengdu Boe Optoelectronics Technology Co., Ltd., Sichuan Province, CN;

Boe Technology Group Co., Ltd., Beijing, CN;

Inventors:

Liang Song, Beijing, CN;

Long Jiang, Beijing, CN;

Mingwen Wang, Beijing, CN;

Pengyu Liao, Beijing, CN;

Zhong Lu, Beijing, CN;

Yuanjie Xu, Beijing, CN;

Benlian Wang, Beijing, CN;

Lili Du, Beijing, CN;

Donghua Jiang, Beijing, CN;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H10D 86/40 (2025.01); H01L 21/77 (2017.01); H10D 86/01 (2025.01); H10D 86/60 (2025.01);
U.S. Cl.
CPC ...
H01L 21/77 (2013.01); H10D 86/0231 (2025.01); H10D 86/441 (2025.01); H10D 86/60 (2025.01);
Abstract

Embodiments of the disclosure disclose a display substrate, a manufacturing method thereof and a display apparatus. The display substrate includes: a base, having a wire routing region; a first wire routing layer, located on the base, where the first wire routing layer in the wire routing region includes a plurality of first routing wires arranged at intervals, and a space between adjacent first routing wires is smaller than 2 um; an insulation layer, located on a side of the first wire routing layer facing away from the base and having a plurality of first via holes corresponding to the first routing wires; a first flat layer, located on a side of the insulation layer facing away from the base and having second via holes corresponding to the first via holes, where the second via holes at least partially overlap with the first via holes.


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