The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 08, 2025

Filed:

Apr. 29, 2022
Applicant:

Denso Corporation, Kariya, JP;

Inventors:

Akihiko Teshigahara, Kariya, JP;

Megumi Suzuki, Kariya, JP;

Assignee:

DENSO CORPORATION, Kariya, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/266 (2006.01); H01L 21/78 (2006.01); H10N 30/074 (2023.01); H10N 39/00 (2023.01);
U.S. Cl.
CPC ...
H01L 21/266 (2013.01); H01L 21/78 (2013.01); H10N 30/074 (2023.02); H10N 39/00 (2023.02);
Abstract

A method for manufacturing an element forming wafer includes the steps of: forming a thin layer on a semiconductor wafer having a plurality of chip forming regions; and adjusting stress generated in an element forming portion of the thin layer to have a specified value. The thin layer constitutes an element in each of the plurality of chip forming regions. The step of adjusting the stress includes: arranging a resist on the thin layer; exposing the resist to light using a photomask having openings; forming openings in the resist by developing the resist; and performing ion-implantation using the resist as a mask. The photomask used during the step of exposing the resist to light has a ratio of the openings that is adjusted based on the stress generated in the element forming portion.


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