The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 08, 2025

Filed:

Mar. 10, 2022
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Yoshinori Fujiwara, Boise, ID (US);

Kristopher Kopel, Boise, ID (US);

Kosei Kudo, Kanagawa, JP;

Assignee:

Micron echnology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/00 (2006.01); G11C 11/408 (2006.01); G11C 11/4094 (2006.01); G11C 11/4097 (2006.01); H03K 19/20 (2006.01);
U.S. Cl.
CPC ...
G11C 29/76 (2013.01); G11C 11/4087 (2013.01); G11C 11/4094 (2013.01); G11C 11/4097 (2013.01); H03K 19/20 (2013.01);
Abstract

Embodiments of the disclosure are drawn to apparatuses and methods for dynamic column select swapping. A memory may have a number of sets of bit lines organized into column planes. If a set of bit lines associated with a first address in a first column plane is defective, it may be repaired by reassigning the first address to a redundant set of bit lines in a global column redundant (GCR) column plane. If a set of bit lines associated with the first address in a second column plane is also defective, then swap logic of the memory may swap the first address to a second address and assign it to the set of bitlines in the second column plane. The second address may then also be repaired by being reassigned to the GCR column plane.


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