The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 08, 2025

Filed:

Apr. 30, 2019
Applicant:

Genesys Logic, Inc., New Taipei, CN;

Inventor:

Woon-Sik Suh, New Taipei, CN;

Assignee:

GENESYS LOGIC, INC., NEW TAIPEI CITY, TAIWAN, CN;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06N 3/063 (2023.01); G06F 1/03 (2006.01); G06F 7/50 (2006.01); G06F 7/523 (2006.01); G06F 7/53 (2006.01); G06F 7/544 (2006.01); G06F 9/54 (2006.01); G06N 3/048 (2023.01); G06N 3/08 (2023.01);
U.S. Cl.
CPC ...
G06N 3/063 (2013.01); G06F 1/03 (2013.01); G06F 7/50 (2013.01); G06F 7/523 (2013.01); G06F 7/53 (2013.01); G06F 7/5443 (2013.01); G06F 9/54 (2013.01); G06N 3/048 (2023.01); G06N 3/08 (2013.01);
Abstract

A convolution block array for implementing neural network application, a method using the same, and a convolution block circuit are provided. The convolution block array includes a plurality of convolution block circuits configured to process a convolution operation of the neural network application, wherein each of the convolution block circuits comprises: a plurality of multiplier circuits configured to perform the convolution operation; and at least one adder circuit connected to the plurality of multiplier circuits and configured to perform an adding operation of results of the convolution operation and generate an output signal; where at least one of the convolution block circuits is configured to perform a biasing operation of the neural network application.


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