Handling eviction write operations caused by rate-limited traffic

Abstract

Techniques are disclosed relating to memory controllers and rate-limited traffic. In some embodiments, an apparatus includes memory controller circuitry configured to satisfy different quality-of-service parameters for multiple different classes of request traffic. The apparatus may also include multiple agents configured to send requests to the memory controller circuitry, where the agents operate according to a rate limit for a first class of traffic. The apparatus may include cache circuitry. In some embodiments, based on an allocation in the cache circuitry for a read operation of the first class that causes an eviction from the cache circuitry, the control circuitry is configured to perform a write operation of evicted data: as the first class of traffic and without counting the write operation toward the rate limit for the first class of traffic. In contrast, the control circuitry may count other write operations of the first class of traffic toward the rate limit.