Optimizing method, device and non-transient computer readable medium for integrated circuit layout

Abstract

An optimizing method, device and non-transient computer readable medium for an integrated circuit layout are provided. The method includes: identifying power rails and corresponding power supply domains in an integrated circuit design file; performing design rule check for circuit units in the integrated circuit design file to calculate a plurality of usable regions; determining electromigration violation points corresponding to the power rails and related current information; defining, according to the electromigration violation points and the current information, paths to be corrected on the power rails corresponding to the electromigration violation points; replacing types of vias on the power rails that do not overlap with the paths to be corrected; and correcting a number of the vias on the power rails that overlap with the paths to be corrected to reduce a number of the electromigration violation points.