The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 08, 2025

Filed:

May. 05, 2022
Applicant:

Google Llc, Mountain View, CA (US);

Inventors:

Robert Coleman Springer, Iv, San Jose, CA (US);

Christopher Daniel Leary, Sunnyvale, CA (US);

Assignee:

Google LLC, Mountain View, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/3323 (2020.01); G06F 30/323 (2020.01); G06F 30/327 (2020.01); G06F 30/367 (2020.01); G06F 30/398 (2020.01); G06F 119/12 (2020.01);
U.S. Cl.
CPC ...
G06F 30/3323 (2020.01); G06F 30/327 (2020.01); G06F 30/323 (2020.01); G06F 30/367 (2020.01); G06F 30/398 (2020.01); G06F 2119/12 (2020.01);
Abstract

Methods, systems, and apparatus, including computer programs encoded on computer storage media for performing logic equivalence check on a circuit design are described. In one aspect, a method includes receiving a request for performing operations of a logical equivalence check of a circuit design and determining, based on one or more criteria, to perform the operations using pipeline stages. In response to the determination, a plurality of pipeline stages of the circuit design that is in a high level representation are determined. For each stage of the plurality of pipeline stages, data corresponding to a high level representation of the stage are obtained, and data corresponding to a low level representation of the stage that corresponds to the high level representation of the stage are obtained. The high level representation and the low level representation are compared. An output is generated based on the comparison.


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