The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 08, 2025

Filed:

Jul. 26, 2023
Applicant:

Western Digital Technologies, Inc., San Jose, CA (US);

Inventors:

Manoj M. Shenoy, Bangalore, IN;

Lakshmi Sowjanya Sunkavelli, Bangalore, IN;

Gopu S, Bengaluru, IN;

Binoy Jose Panakkal, Bengaluru, IN;

Assignee:

Sandisk Technologies, Inc., Milpitas, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0652 (2013.01); G06F 3/0608 (2013.01); G06F 3/064 (2013.01); G06F 3/0679 (2013.01);
Abstract

A three tier memory has an upper sub block, a lower sub block, and a middle sub block. In the present disclosure, rather than precharging the upper and lower sub blocks, use is made of the middle sub block using a firmware (FW) scheme. Upon receiving a write request from a host, the FW will route the data to the middle sub block (SB) through reverse order programming (ROP) so that the SBis pre-charged through the source side through the lower sub block (SB). Once the SBis written, data is then routed to the SBand then to the upper sub block (SB). When there is a garbage collection (GC) request, the FW will move the data from the SBand then erase the SB. Then the data moves from the SBand SBis erased. Finally, the data moves from the SBand then SBis erased.


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