The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 08, 2025

Filed:

Sep. 06, 2023
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Panchami Devashya Shivarama, San Diego, CA (US);

Ying Duan, San Diego, CA (US);

Qinqing Cao, San Diego, CA (US);

Seuk Son, San Diego, CA (US);

Mansoor Basha Shaik, Bangalore, IN;

Abhay Dixit, San Diego, CA (US);

Assignee:

QUALCOMM INCORPORATED, San Diego, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 13/42 (2006.01); G06F 13/40 (2006.01);
U.S. Cl.
CPC ...
G06F 13/4282 (2013.01); G06F 13/4068 (2013.01);
Abstract

An input buffer includes a pair of input transistors and associated injection circuits. A first input transistor has a source coupled to a first voltage rail through a first current source and a gate coupled to a first wire of a multi-wire serial bus. Three or more resistors in a first injection circuit couple the wires of the serial bus to a first common node, which is coupled to the source of the first input transistor by a first capacitor. A second input transistor has a source coupled to the first voltage rail through a second current source and a gate coupled to a second wire of the serial bus. Three or more resistors in a second injection circuit couple the wires of the multi-wire serial bus to a second common node, which is coupled to the source of the second input transistor by a second capacitor.


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