The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 08, 2025

Filed:

Aug. 31, 2023
Applicants:

Advanced Micro Devices, Inc, Santa Clara, CA (US);

Ati Technologies Ulc, Markham, CA;

Inventors:

Kishore Punniyamurthy, Austin, TX (US);

Richard David Sodke, Kelowna, CA;

Furkan Eris, Sunnyvale, CA (US);

Sergey Blagodurov, Bellevue, WA (US);

Bradford Michael Beckmann, Kirkland, WA (US);

Brandon Keith Potter, Troup, TX (US);

Khaled Hamidouche, Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/02 (2006.01); G06F 13/16 (2006.01); G06F 13/28 (2006.01); G06F 13/40 (2006.01);
U.S. Cl.
CPC ...
G06F 12/023 (2013.01); G06F 13/1673 (2013.01); G06F 13/28 (2013.01); G06F 13/4022 (2013.01); G06F 13/404 (2013.01);
Abstract

A device includes a plurality of processing elements (PEs). A symmetric memory is allocated in each of the plurality of PEs. The device includes a switch connected to the plurality of PEs. The switch is to: receive, from a first processing element (PE) of the plurality of PEs, a message that includes a buffer offset, compute, based on the buffer offset, a first memory address of a first buffer in a first symmetric memory of the first PE and a second memory address of a second buffer in a second symmetric memory of a second PE of the plurality of PEs, and initiate, based on the first memory address and the second memory address, a direct memory access operation to access the first buffer and the second buffer.


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